Recent reductions in the field pitch of DRAM cells have been accompanied by difficulties in maintaining the channel width W of memory cell transistors, which have led to reduced transistor characteristics and adverse effects on read characteristics, refresh characteristics, and other important characteristics of DRAM. Miniaturization of DRAM cells has also caused the aspect ratio of vertical transistors to increase, and resulted in significant problems such as increased contact resistance or connection defects between cell contacts and source/drain regions, and reduced processing margins in SAC (Self Align Contact) or etching. The field pitch of the currently mass-produced DRAM having a cell area of 6F2 has recently been reduced to less than that of identically designed DRAM having a cell area of 8F2. Therefore, maintaining the transistor characteristics has become even more rigorous.
Therefore, a method has recently been proposed in which the active region is caused to protrude beyond the element isolation region, and the side surfaces of the active region thus formed are utilized to maintain the channel width W (see Japanese Laid-open Patent Application No. 2001-35983). This method makes it possible to maintain a wider channel width W while the field pitch remains constant. In other words, the field pitch can be significantly reduced without adversely affecting the transistor characteristics.
A method has also been proposed in which a silicon substrate is built up by selective epitaxial growth (SEG) to form a silicon epitaxial layer on the source/drain regions (see Japanese Laid-open Patent Application No. 2005-109346). This method makes it possible to ensure an electrical connection between the source/drain regions and the cell contacts, suppress short-channel effects in a memory cell transistor, and suppress increases in contact resistance or bit-line capacity (Cb).
However, since selective epitaxial growth is a technique for selectively growing silicon crystals on a silicon substrate, there is a risk of short-circuiting between adjacent epitaxial layers, depending on the direction of silicon crystal growth. Particularly in a silicon substrate having protruding active regions, growth progresses in the transverse direction of the silicon epitaxial layer in the side surfaces of the active regions, and short-circuiting easily occurs between adjacent silicon epitaxial layers.
FIG. 39 is a schematic plain view showing the planar layout of a conventional DRAM cell transistor; FIG. 40A is a schematic cross-sectional view along line P-P in FIG. 39; FIG. 40B is a schematic cross-sectional view along line Q-Q in FIG. 39; and FIG. 40C is a schematic cross-sectional view along line R-R in FIG. 39.
As shown in FIG. 39, the active regions 13 on the silicon substrate 11 are elongated narrow island regions encircled by element isolation regions 12, and the longitudinal direction of the active regions 13 is at a prescribed angle in relation to the direction (X direction) orthogonal to the wiring direction of the word lines (gate electrodes) 15. The plurality of active regions 13 is arranged in a straight line in the longitudinal direction thereof, and is also arranged at equal intervals in relation to the wiring direction (Y direction) of the word lines 15. As shown in FIGS. 40A through 40C, the surfaces of the active regions 13 protrude beyond the element isolation regions 12, and the lateral surface portions of the active regions 13 are utilized to maintain a wider channel width W. The active regions 13 shown in the drawings are rounded active regions whose side surfaces have a gradual rise.
As shown in the drawings, impurity diffusion regions are formed on the exposed surfaces of the active regions 13 not covered by the word lines 15, but silicon epitaxial layers 19 are formed directly above the impurity diffusion regions, and cell contacts 22 are formed directly thereon. Furthermore, bit lines 24 extending in the X direction are wired in a layer above the cell contacts 22. The bit lines are wired in meandering fashion so as to pass over the cell contacts 22 at the center of the active regions 13 and to avoid the cell contacts 22 at the both ends of the active regions 13.
As shown in FIG. 40B, when the side surfaces of the active regions 13 are exposed, the silicon epitaxial layers easily grow not only in the direction perpendicular to the substrate surface, but also in the parallel direction (Y direction). When the silicon epitaxial layers grow in this fashion, there is a risk of short-circuiting between adjacent silicon epitaxial layers 19, 19. It may appear that this problem can be overcome by stopping the growth of the silicon epitaxial layers before short-circuiting occurs between the silicon epitaxial layers 19, 19, but an adequate thickness of the silicon epitaxial layers 19 cannot be maintained in this case, and it becomes difficult to suppress short-channel effects in the memory cell transistor. There is therefore a need for a new method for reliably preventing short-circuiting between silicon epitaxial layers that are adjacent to each other.